The present invention relates generally to the field of processor design, and more particularly to design of “standard cells” used in processor design.
When manufacturing sophisticated devices, such as integrated circuits on chips, many factors in the design and manufacturing process can affect the performance and operability of the devices. One factor that has been found to play a role in high quality integrated circuit devices relates to the timing differences of communication and other signals as they travel across the circuits. Therefore, it is common to find and test the “timing paths” within the circuit along which the various signals will travel to ensure that the most important paths or bottleneck paths (for example, the critical timing paths) operate properly.
In processor design methodology, a given signal path will have some relative degree of “speed” depending upon factors such as delay imparted by circuitry components through which the path passes the signal and/or path length. Accordingly, there are relatively fast paths (or fast arcs) and relatively slow paths (or slow arcs). Sometimes a fast path signal and a slow path signal should ideally arrive at a common destination (such as a logic gate) at the same time, but they do not arrive simultaneously because one signal is faster than the other. This is called “delay.” Conventionally, delay is dealt with clocks and timers that determine when the fast and slow signals can be received by the circuitry (such as a logic gate) that is supposed to receive the two signals simultaneously. In some conventional solutions, “standard cell methodology” is used in designing circuitry that uses clocks and/or timers to account for relative delay among multiple input signals received at a logic gate.
Slow paths usually have excessive logic to traverse between the launching and capturing latch. Fast paths have lesser logic to traverse through before reaching the capturing latch. Thus, there exists a risk of the “fast” signal being too fast and passing through multiple latch stages in a single clock cycle. Fast paths are addressed by varying the following in the affected timing path: (i) drive strength; (ii) signal routing; (iii) wire placement; and/or (iv) wire dimensions. Fast paths can further be addressed by introducing specific slow (or delay) cells which increase the delay in the path. The time lag of a slow path signal, relative to a fast path signal, is sometimes herein referred to as a “timing slack.”
As referenced above, network delay is one design and performance characteristic to be considered in a computer network. The delay specifies how long it takes for a bit of data, or signal, to travel across the computer network from one endpoint (node) to another. The delay is typically measured in fractions of seconds, such as picoseconds (ps). Electronic logic gates used in circuit design can exhibit different “logical efforts” for different inputs. These types of gates are called asymmetric gates. Asymmetric gates can increase or decrease critical path speed in a network by changing the “logical effort” along the critical path of the circuit.
Another design approach is the use of early mode padding. The goal is to ensure that signals do not “fly through” multiple stages in one (1) clock cycle. Some conventional methods to prevent “fly through” are as follows: (i) using variable delays along different GCLK (global clock) to latch paths; (ii) using transparency window of latches; (iii) incorporating latch clock timing circuits; (iv) the use of logic gates; and/or (v) applying several stages of logic.